A phase locked loop (PLL) implemented with an integrated circuit (IC) provides an efficient tool in implementing high-frequency local oscillator and clock signals for radio transceivers in telecommunication systems. A phase locked loop is known as a feedback system for providing electric signals that are accurate in frequency and stable in phase. A typical phase locked loop includes a voltage controlled oscillator (VCO), an analog loop filter, a charge pump, a phase-frequency detector unit and a frequency divider with a frequency division ratio (M) in a feedback loop. The voltage controlled oscillator is set into a negative feedback control loop which forces it to oscillate in a frequency defined with the frequency divider and a given reference frequency Fref.
In a conventional charge-pump based phase locked loop, the stability and the settling performance of the loop are defined by the gain of the voltage controlled oscillator, the division ratio of the frequency divider, gain of the phase-frequency detector and the charge pump, and the frequency response of the analog loop filter. FIG. 1 shows an example of the implementation of the analog loop filter. C1 is the capacitor integrating the current pulses generated by the charge pump. With proper design, dominant time constants introduced by the C1, C2 and R1 can be set so that the phase locked loop is stable in all conditions with a desired closed loop bandwidth and loop settling time. R2, C3, R3 and C4 form high frequency poles that have minor impact on the settling behavior and stability of the loop.
However, a problem with the traditional analog filter design is that with practical implementations for communications systems the loop filter takes a quite a lot of space in silicon. Another alternative is to use external components which increase the circuit board area and cost. This is especially problem with fractional phase locked loops where M is low and the loop filter impedance level has to be relatively low for gaining the suitable values for charge pump current and VCO gain. This leads to large capacitance values for C1 and especially for C2, of which value is typically around 10 times higher than C1 when the loop is designed for a radio transceiver used in a mobile communication device.